1. Field of the Invention
The present invention relates to a flip-chip type semiconductor integrated circuit device in which pads are arranged on an entire semiconductor chip to connect the semiconductor chip to a package.
2. Description of the Related Art
Conventionally, there has been provided a flip-chip type semiconductor integrated circuit device in which pads are arranged on an entire semiconductor chip to connect the semiconductor chip to a package.
FIG. 16 shows a plan view of a flip-chip type semiconductor integrated circuit device according to the first prior art. FIG. 17 shows a partially enlarged view of the semiconductor integrated circuit device shown in FIG. 16. Interconnections are omitted in FIG. 16. The flip-chip type semiconductor integrated circuit device according to the first prior art will be described below.
As shown in FIG. 16, pads (or bumps) 12 for electrical connection to a package (not shown) are arranged on an entire chip 11, and rectangular I/O cells 13 are arranged along the sides of the chip 11. The pads 12 on the center of the chip 11 are used for supplying a power supply voltage and ground potential to an internal circuit, and the pads 12 on the peripheral portion of the chip 11 are used for supplying signals, a power supply voltage, and a ground potential to the I/O cells 13. Internal signal terminals 13a connected to the internal circuit of the chip 11 are formed on the end portion of each I/O cell 13 on the center side of the chip 11, and an external signal terminal 13b connected to each pad 12 is formed on the end portion of each I/O cell 13 on the peripheral side of the chip 11.
As shown in FIG. 17, since a distance between the pads 12 is longer than the length of a general I/O cell 13, the pads 12 in a plurality of columns are assigned to the I/O cells 13 in one column. The pads 12 and the external signal terminals 13b of the I/O cells 13 are connected to interconnections 15. The interconnections 15 are formed from only one uppermost layer which is a thickest layer, or two layers, the uppermost and next layers. The pads 12 on the center of the chip 11 are respectively connected to power supply interconnections 17 and ground interconnections 18.
In the first prior art described above, when the number of signal terminals must be increased along with an increase in number of the input/output signals, since the I/O cells 13 are arranged along the sides of the chip 11, the chip 11 must be enlarged to increase the number of I/O cells 13 that can be arranged. To increase the number of signal terminals without enlarging the chip 11, the following second prior art is disclosed.
FIG. 18 shows a plan view of a flip-chip type semiconductor integrated circuit device according to the second prior art. FIG. 19 shows a partially enlarged view of the semiconductor integrated circuit device shown in FIG. 18. Interconnections are omitted in FIG. 18. The flip-chip type semiconductor integrated circuit device according to the second prior art will be described below.
As shown in FIG. 18, similar to the first prior art, pads 12 for electrical connection to a package (not shown) are arranged on an entire chip 11, and rectangular first I/O cells 13 are arranged along the sides of the chip 11. In addition, second I/O cells 14 are arranged inside the first I/O cells 13. This enables, without enlarging the chip 11, to arrange the I/O cells 13 and 14 larger in number than those in the first prior art, thereby increasing the number of signal terminals.
In the second prior art described above, as shown in FIG. 19, some second interconnections 16 which connect the second I/O cells 14 to the pads 12 on the center of the chip 11 are long, resulting in an increase in resistance and capacitance of each prolonged second interconnection 16. In addition, the second interconnections 16 connecting the second I/O cells 14 to the pads 12 and the first interconnections 15 connecting the first I/O cells 13 to the pads 12 are crowded on the narrow regions between the pads 12 above the second I/O cells 14. When the plurality of interconnections 15 and 16 are crowded in such narrow regions, and in particular, the interconnections 15 and 16 are formed from only one uppermost metal interconnection region, no interconnections 15 and 16 having an enough width each can be formed.
As described above, in the first and second prior arts, it is difficult to shorten the interconnections 15 and 16 and relax the crowd thereof while increasing the number of I/O cells 13 and 14.